IMPLEMENTING WITH UART

[sridivya]

hiii...i mean , i am unable to capture the waveform as per the character given in UART.....SO CAN U TELL ME WHERE THE CHANGES TO BE MADE???

[bobmarlowe]

Still not understanding what you mean, sorry that's a language problem.
Upload project and based on the pins, what is your problem?

Bob

[sridivya]

Hi..i have a doubt that in AN2336 FSK is implemented through PWM..and that analog signaling is used...but for the input to pwm..there is no analog wave provided...can u explain it???

[bobmarlowe]

Going through the AN2336 i can say:
The PWM is used ONLY for clock generation to get a precise independant clock. The FSK-decoding works exactly as described in the PDF-File of the application note and when looking at your scope-pictures I cannot see any ambiguities.
Have a look at the schematic on page 7 (PDF of AN2336) to see the signal flow with the pins.

Bob

[sridivya]

hii..my doubt is that as in AN67391 , The input to the PWM_0 and PWM_1 are the digital inputs right..but as per the communication defintion , the input must be an analog signal for the pwm...so please justify???

[bobmarlowe]

Now you are talking about a different AN, can you please stick to one topic? The input of a PWM is NEVER EVER an analog signal, the only input a PWM has is the clock. An analog signal may be amplified to the rails and then used (best is together with a schmitt-trigger) as a digital input. As I remember this is done in the FSK-examples, but as I explained the last time, the signal is not fed into a PWM but into a diskriminator that decides if it is low or high frequency.

Bob

To let me better help you, post a project or a picture or a link to an AN-PDF-file and ask a concrete question, it is very difficult for me to follow your thought without knowing what you are EXACTLY talking about.

[sridivya]

hiii..as in the AN67391 application , FSK is generated by using PWM. my question is that , as per the definition in communication , pulse width is varied in accordance with the analog input modulating signal. but the PWM used here has only the digital inputs...no analog signal is provided to PWM.. So i need to know that whether the PWM used in PSoC is different from the PWM used in analog communication system???? has it been called the digital PWM??? Im sending a zip file which includes block diagram of AN67391 application

[bobmarlowe]

That is something I can work with!
The input "Data In" is a digital signal (usually this signal is the output of an UART) that switches between the two frequencies generated by the two PWMs. With the XOR they are combined to one signal which now is at high or low frequency depending on the "Data In" beeing high or low.

The PWM3 takes the high/low frequency and divides it down and deliveres a DIGITAL FSK signal, NOT ANALOG!!!
The conversion to an analog signal is not shown in your attached picture, but as I remember there was a band-pass-filter (BPF) used to generate a sine-wave out of the digital signal.

PWM in general is a digital module and there is no difference from PSoC PWMs to any other.
You find applications, where the output of a PWM is connected to an RC-ladder to retrieve an analog voltage depending on the duty-cycle of a PWM, but that is not used here within your FSK-example.

Hope that clarifies
Bob

[danadak]

The result pictures basically look correct, although you might consider
an analog scope as a verification no aliasing is occuring due to scope
sampling rate if a low performance DSO.

I do see evidence you may have 60/120 Hz AM of the filter output, or
a ground loop with scope ground creating a ground moving with line
frequency. You might either float the scope ground, or better yet use
scope in diff mode, one channel on ground, one on filter out, and
invert one channel, scope mode set to add. That would get rid of CM
noise, in this case 60/120 Hz. Note scope in this mode has a spec for
CMRR itself, so look that up as it affects how much of the CM compo-
nents scope can reject. Remember to cal the probes as they also, if not
matched, affect CMRR in this mode.

http://www.cbtricks.com/miscellaneous/tech_publications/scope/floating.pdf

DiffOscMeasurements.pdf

(214.47 KiB) Downloaded 24 times

The oversample clock is directly responsible for the filter pole/zero
locations, hence response, the wizard handles this for you. The res-
ponse of the filter controls the harmonic content in the filter output.
Clearly you want to reject harmonics as much as possible. So make sure
filter peak response occurs at freq of interest, the FSK value, and that
its BW/Q appropriate for harmonic rejection you are trying to achieve.

Also be carefull signal path gain thru any amp and filter do not saturate
the filter output swing. In this case G << 1 as the output buffer does not
swing rail to rail, if you overdrive any element in signal path that produces
distortion.

Also pay attention to data sheet graphs for peak voltage vs parameters, like
frequency,.....

Regards, Dana.

[sridivya]

bob , as u said that there is no difference between PSoC pwm's and other , i have a doubt that generally, pwm have the analog data as input ; according to that the pulse variations are done ; right????but in PSoC the pwm has the digital data as input...

[bobmarlowe]

No, you're not right. The implementation of a PWM may differ from model to model, but (yet) I've not seen a PWM with an analog input (except for analog-to-digital-converters). As you see, this PWM has no "Input" except the clock (which EVERY PWM must have) , all controls are internal and may be altered by CPU.

And again: in the PSoC example the PWM has NOT the digital data as input!!!!!!!!! It is really the same as if you use a multiplexor to select one of two frequencies, here you ENABLE one of the two generated frequencies. You could have used a timer-module instead with the very same functionality if the timer had an enable input(which it lacks).

Bob