Nested interrupts

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Nested interrupts

Postby shazan » Tue Dec 03, 2013 3:57 am

Hi
I am trying to run my system with 3 interrupts:
1. A timer int of low priority every 125ms, during which I enable interrupts to allow the second one to run without delay.
2. a 200uS interrupt from DBC01, which is normally of the highest priority and during which - till now - I had disabled global interrupts. So far so good. No issues till now, and things work smoothly.
3. Now I want to add an interrupt which will be of the highest priority, which means it should be capable of interrupting the two mentioned above. This third interrupt I will take from the analog column 0 interrupt. My doubt is:
How do I enable only the third interrupt (as well as other highest priority interrupts) during the second interrupt? I didn't understand the mask registers and the clear registers. posted?? pending?? cleared?? masked??....I am flummoxed, so will be really appreciative if some of you experienced PSoC veterans would explain the way I should go about this?
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Re: Nested interrupts

Postby bobmarlowe » Tue Dec 03, 2013 6:04 am

First of all: 5000 interrupts per second is going to exhaust the capabilities of the PSoC1 CPU. Much care must be taken not to use more MIPS than availlable.

Next: You cannot change or assign interrupt priorities in a PSoC1 look here. As you see here they are distributed automatically.

The mechanism works as follows: When the appropiate interrupt handler is entered, interrupts are disabled automatically. You may re-enable interrupts at any time back again. When the handler finishes, interrupts are restored to the state when the handler was entered (which MUST be "enabled" or the handler could not have been called).

A solution could be to indicate with a flag that the highest priority-handler is running and so forcing lower priorities to early-exit. This can be done also by masking the unwanted interrupts in the ICU and restoring the original mask which will fire the interrupt at the next possible moment.


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Re: Nested interrupts

Postby shazan » Tue Dec 03, 2013 7:32 am

bobmarlowe wrote:...This can be done also by masking the unwanted interrupts in the ICU and restoring the original mask which will fire the interrupt at the next possible moment.
Bob


TY Bob. So in the 200uS ISR, if I mask OFF all the other bits except for the Analog column interrupt and voltage monitor interrupts, then if I enable global interrupts, I should be good to go? This will mean 4 or 5 more instructions on entry into the 200uS ISR. The highest priority int is a fault/failsafe int, so my system will restart or halt after this takes place.

First of all: 5000 interrupts per second is going to exhaust the capabilities of the PSoC1 CPU. Much care must be taken not to use more MIPS than availlable.

I make sure the ISR time is well used. No calculations, save a few additions, indexes, compares. My 200uS ISR takes around 100uS, with all overheads. The work outside the 200uS ISR is all slow, real time stuff. Seconds don't matter, though I will need to trim the RTC registers to make it close to real time.
But how do I make the PSoC work at higher MIPS? I am using the 24MHz clock, and the CPU is at Sysclk/1. How do I make sure the MIPS are not exceeded?
I mean, taking CPU clock at 24MHz, the cycle time comes to 41nS, while 4MIPS at 24MHz works out to 250nS per instruction, which means the instructions that use 6+ cycles are okay, but what about the smaller/faster instructions? What is the end result if I run the system at higher MIPS than 4?
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Re: Nested interrupts

Postby bobmarlowe » Tue Dec 03, 2013 8:00 am

There are some simple considerations when strapping down ISR-handlers:

Use #pragma interrupt_handler YourHandler (refer to C Language Compiler User's Guide) and provide your own routine(s) in main.c
in Boot.tpl place a LJMP _YourHandler, do NOT use macro to preserve CPU-state
ABSOLUTELY NO function-calls inside handler!!!
Avoid switch-statement
Use static variables allocated in page 0, avoid local vars. Remember to initialize static vars in code, not at declaration.

Happy coding!
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Re: Nested interrupts

Postby BitBangerB » Fri Feb 28, 2014 9:48 am

For the record, I have an interrupt that runs at 14400 times per second. And, I am limited to 12 MHz. That allows up to 832 cycles per IRQ which is quite a lot. I don't see your 5000 as being a problem unless you are trying to do too much.

In my system, I have multiple interrupts at varying rates. I don't pay much attention to the built-in priority structure. Rather, I allow certain interrupts to run with interrupts enabled. Normally, upon entry to an interrupt the GIE flag is automatically set to disabled, preventing others from coming in until the current one completes. There is no reason you cannot re-enable interrupts inside an interrupt handler so that higher priority interrupts may be serviced.

There are caveats however!

Once interrupts are enabled inside an interrupt, the possibility arises that a given interrupt may interrupt itself. This may lead to disaster if not handled properly. In my case, it would not be normal for an interrupt to interrupt itself. However, I protect against the possibility by checking and then setting a 'NO REENTRY' flag at the very beginning of the IRQ handler. If the flag is set, the IRQ just exits.

I hope this helps!

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