Question about the analog values limits

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Question about the analog values limits

Postby AI18 » Wed Feb 19, 2014 3:51 pm

The attatched photo is from the AN2168 (PSoC® 1 Understanding Switched Capacitor Filters) page 10
the reference voltage is 1.3 v and the negative peak is 2v so it will go under 0 volt, is that ok ?!!
Excuse me, I'm new to the PSoC world
thanks alot
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Vpp & analog ref.PNG
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Re: Question about the analog values limits

Postby bobmarlowe » Thu Feb 20, 2014 2:51 am

No, that's not ok. No pin may have a voltage applied to less than GND. Probably a mis-understanding or mis-explanation in the AppNote.

Bob
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Re: Question about the analog values limits

Postby danadak » Thu Feb 20, 2014 6:53 am

Attached some techniques of handling - voltage swings.

The reason for the limitation is a parasitic SCR structure that exists
in CMOS, a negative swing can trigger it, and it shorts internally the
Vdd and Vss rails. Can blow out the chip bond wires, at minimum draw
a lot of current and overheat part.

ADinput negative inputs.zip
(87.24 KiB) Downloaded 150 times


Regards, Dana.
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Re: Question about the analog values limits

Postby AI18 » Fri Feb 28, 2014 9:48 am

Tanks alot Bob and Dana
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