CY8CLED04D01 Power PSoC CSA Vsense Question

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CY8CLED04D01 Power PSoC CSA Vsense Question

Postby georgemo » Tue Aug 04, 2009 3:00 pm

Hello,

I'm working on my first Power PSoC design using a CY8CLED04D01. I'm trying to pick sense resistors that are good for 0.7A to 3.0A which would allow me to run all my varied LEDs. Application note 51012 on page 7 states that the Vsense developed across the Rsense should be 50mV to 300mV. If I pick Rsense=75mOhms, CSA gain = 4, and DAC V range = 1.3V (assuming 20% current ripple), then my Vsense should run from about 58mV to 248mV. I thought I was good until I noticed a line in the PowerPSoC datasheet, page 31, listing Vsense from 0mV to 150mV. Those two sets of numbers are pictured below.

Image

Even more confusing, just below the datasheet Vsense line it shows, "Vsense = 50 mV to 130 mV." Does AN51012 have a typo where it should be 50mV to 130mV instead of 50mV to 300mV? That's my concern.

My DAC values are within the 0-255 range. They go, in decimal, from 37 to 194, so I guess it's ok. But I don't want to screw up my first PowerPSoC design.

Thanks for any comments,
George
Last edited by georgemo on Thu Dec 24, 2009 8:37 am, edited 1 time in total.
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Re: CY8CLED04D01 Power PSoC CSA Vsense Question

Postby yzr » Wed Aug 05, 2009 5:47 am

georgemo,
The content in the application note is a typo. I shall work on having the fixed. The range of the CSA is indeed 0-150mV. The PPSoC CSA has a calibrated gain of 20 and the DACs have a mapping upto 2.6V.
Thus, inorder to increase the resolution, the current sense resistor should be chosen such that R * Current * 20 < 2.6V. In order to optimize the current resolution and make room for any overshoots based on the magnetics chosen, it is best to have R * Current * 20 ~= 2.4V. In addition to the 8-bit current control, you can use 16-bit of digital dimming control.
If your circuit card is designed to work for the range of 0.7A to 3A, the current used for the calculations above should be 3A.
As a lighting focused Engineer at Cypress, I have come across a few boards where the layout of the high current loop caused significant problems in the design. The attached App Note (AN522091 PCB Guidelines for PPSoC as a LED Driver) may aid you during the layout process. If you are interested in having your design files reviewed by Cypress, feel free to get in touch with me at yzr@cypress.com.
Regards
yzr
Attachments
AN522091 PCB Guidelines for PPSoC as a LED Driver.pdf
PCB Guidelines for PPSoC
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Re: CY8CLED04D01 Power PSoC CSA Vsense Question

Postby yzr » Wed Aug 05, 2009 5:57 am

georgemo,
Also, please note that though the gains of 3,4,15 and 20 are available, only gain of 20 is calibrated for current accuracy. This will be clarified in revisions of User Module datasheet as well as Application Notes.
-yzr
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Re: CY8CLED04D01 Power PSoC CSA Vsense Question

Postby georgemo » Wed Aug 05, 2009 9:47 am

yzr,

Thank you very much for the fast and informative response. I will read AN522091 and redo my calculations.

I sent in a tech support case asking the following:

Case 26VF1HI wrote:I'm designing a PCB for a PowerPSoC for the first time. I'm using external FETs as in figure 6-2 of the datasheet. The figure does not illustrate how to handle the unused internal FET pins (SW0-SW3, pins 40, 37, 36, 33, respectively). Should I tie them to ground, float them, etc.?


It's been a few days without a response. Do you happen to know the answer?

Thank you very much,
George
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Re: CY8CLED04D01 Power PSoC CSA Vsense Question

Postby yzr » Sat Aug 08, 2009 6:57 am

George,
It appears that there was an issue with the email notification when the tighlink question was answered.
As indicated by the Apps team, the SWx pins can be left floating.
Rakesh
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