CY8CLED04D01 Power PSoC Modulation Question

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CY8CLED04D01 Power PSoC Modulation Question

Postby georgemo » Thu Aug 20, 2009 1:12 pm

Hello,

In a previous project I implemented a Manchester encoder in a CY8C24894 and output it as the DIM control to a National Semiconductor CCS LED driver. I bought a CY3268 and would like to implement all of the previous design inside a CY8CLED04D01 Power PSoC. Ideally, I need to operate two of the channels with 100k-200k "Manchester-encoded PWM" and the other two channels with normal but slow PWM. I have a few questions.

1) If I implement the Manchester encoder, can I route its output from the GlobalOut lines to the Hysteretic Controller's DimInput? I see only MODx and FN_0_x options for DimInput. Will I have to install an external jumper from say P0[5] to FN_0_0, or is there a way to connect it internally?

2) Looking at the 16-Bit Hardware Pulse Width Modulator UM datasheet, if I use the 24MHz system clock with a Clock Scaler of 256 (max) and 16-bit PWM, then the minimum PWM frequency should be 1.43 Hz, right?


Thank you in advance for any clarifications,
George
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Re: CY8CLED04D01 Power PSoC Modulation Question

Postby georgemo » Fri Aug 21, 2009 6:44 am

I tried adding the Manchester encoder parts to the example project that comes with the CY3268 kit, CY3268_Example1. It had a bunch of errors when I hit Generate after adding two user modules. There were 9 errors due to multiple definitions of the CapSense stuff. I opened the original CY3268_Example1 before I made changes, and it has the same errors. So it was not something I did.

I just tried finding a newer version online, and no example projects or application notes are listed on cypress.com for either the CY3268 or CY8CLED04D01. Does anyone know of an error-free version of the CY3268 demo?


Edit: I just tried the other firmware example, CY3268_Heartbeat, and got the same errors:

Code: Select all
Linking..
!E _62S.AAA(2302): multiple define: '_CSD0_waSnsDiff'
!E _62S.AAA(2303): multiple define: 'CSD0_waSnsBaseline'
!E _62S.AAA(2304): multiple define: 'CSD0_waSnsDiff'
!E _62S.AAA(2305): multiple define: '_CSD0_waSnsBaseline'
!E _62S.AAA(2307): multiple define: '_CSD0_baSnsOnMask'
!E _62S.AAA(2308): multiple define: 'CSD0_baBtnFThreshold'
!E _62S.AAA(2309): multiple define: '_CSD0_baBtnFThreshold'
!E _62S.AAA(2310): multiple define: 'CSD0_baSnsOnMask'
LMM info: ...
...
C:\PROGRA~1\Cypress\Common\CYPRES~3\tools\make: *** [output/CY3268_Heartbeat.rom] Error 1
 
CY3268_Heartbeat - 9 error(s) 0 warning(s) 09:52:57


I'm using PD5.0 "Service Pack 5 - Build 972 - Jun 24, 2009"
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Re: CY8CLED04D01 Power PSoC Modulation Question

Postby yzr » Fri Aug 21, 2009 8:08 pm

Georgemo,

1)The Digital blocks cannot connect directly to the HYST CTRL blocks on the PPSoC chips. You will need to bring it a P0_x pin, connect externally to a FN pin and drive your DIM input with it.
2) Your calculations to get to 1.43 Hz are correct.

The error you are seeing with the CSD User Module is not occurring due to CY3268 Example code but due to an error in the PSoC Designer CSD UM generation in SP5. It has been fixed in SP5.5 onwards.
A workaround while using SP5 is to delete the CSDRAM.asm from the project tree.
Let me know if this helps. You can send me a pm at yzr@cypress.com to expedite any support that you may need.

Regards
yzr
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Re: CY8CLED04D01 Power PSoC Modulation Question

Postby georgemo » Mon Aug 24, 2009 6:44 am

yzr,

Thank you for the response. We're disappointed about the need for external jumpers, but we're otherwise happy with the Power PSoC. I installed SP5.5 (now Service Pack 5.5 - Build 985 - Jul 24, 2009), and now the CY3268 example projects generate and build without error.

Thank you,
George
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