PSoC3 Custom Board

[radner]

Ok I'll try to do so,
by the way how do I get the USB Bootloader on the chip and how do I tell psoc creator that it should build a bootloaderable application?

Best Regards

Phillip

[kmmankad]

There is a USB Bootloader Appnote that should be out soon,(its sad to see it delayed for so long.),and this should help too:

PSoC 3/5 Creator Bootloader Overview Video http://www.cypress.com/?rID=51139

Also,for reference,
AN60317 - PSoC® 3/PSoC 5 I2C Bootloader http://www.cypress.com/?rID=41002

[radner]

I think (and hope) this documents will be available with the release PSOC Creator 2.0

Regards

Phillip

[kmmankad]

Yes,bootloaders and many new examples are included with Creator 2.0.I hope they release it fast.

[radner]

As far as I know the final version should be published this week or week after this week.

And as far as mouser announces availability of PSOC 5 processors for 13th of january the development software for the PSOC 5 processors should be available a few weeks before that, 'cause I don't think mouser is the first one who gets processors out of high volume production

[kmmankad]

For the I2C bootloader,I was wondering if the magic is in the MiniProg3 or it is the bootloader host program that does it,and the MiniProg is just a dumb(by dumb I mean simple to implement on a lowly attiny or similar) USB->I2C pipe.

[radner]

Would be interesting to know but their is no information about this porvided by cypress, or at least I didn't find anything to deal with this issue.

[kmmankad]

After a few valuable inputs from the gurus at Cypress(thanks guys,means a lot to me!),heres the latest batch of changes:

--Added additional vias between the top and bottom layers to improve return paths.
--Crystal routing improved(Capacitors on same side,traces shorter).
--Added reverse polarity protection diode across Unregulated DC Input(VIN).
--Added Fuse to USB supply.
--Added LED for Bootloader Status.
--Widened Power tracks for better stability.
--Differential Routing for SWD and USB tracks.
--Changed back to Type B USB connector,easier to solder.

[radner]

I just did a little imprvement on the reverse battery protection circuit.

I replaced the diode with a p-channel mosfet, for further circuit description see http://www.infineon.com/dgdl/Reverse_Batery_Protection.pdf?folderId=db3a304412b407950112b418872b2614&fileId=db3a304412b407950112b41887722615

This circuit provides higher efficiency than the diode solution and has comparable space and cost requirements.
The Z-Diode and the Resistor is not needed in this case, 'cause as far as I see that whe can't expect 20V transients.

Best Regards

Phillip

[kmmankad]

Ah,nice.I just saw this video the other day,which details a similar solution.Will make the change in the next revision.I've already sent out the boards for manufacture
Here it is :
http://www.youtube.com/watch?v=IrB-FPcv1Dc

[radner]

I'm now ordering the parts for the prototype I'm going to manufacture in the christmas holidays.

Now I asked myself what crystal should I use for the MHz Oscilator?

I would prefer one in the lower frequency range, somewhere between 4 or 5 MHz.
'Cause if we need higher frequencies we can use the on chip PLL and the benefit of it is that the layout isn't that critical.

Best Regards
Phillip

[kmmankad]

Well,about the clocking,the least we can go with is 4Mhz.However,I am not so sure about the crystal routing,since I have connected the capacitors to the crystal,but the crystal to the chip,and not crystal to the capacitors,which then goto the chip,as suggested in the appnote linked below.But then hopefully at 4Mhz,it wont make a large difference.

http://www.cypress.com/?docID=30089

[radner]

This could may 'cause stability problems, alltough I'm not sure if that's a problem at 4 MHz but allways remember as rule of thumb you add 1nH/cm parasitic inductance with the tracks.

But what I see is that you could add 2 vias at the track from the crystal to the processor, so you could place the caps on the bottom side and get a little shorter traces with that.

Best Regards
Phillip

[kmmankad]

But the appnote recommends them to be on the same side.Anyway,the crystal is an optional addition,since the internal clocking is accurate enough for most applications,including USB.

Other devboards I have used seldom implement the above suggested routing,so I guess thats for a very solid,Test & Measurement Industry product,and we can go with some educational error.

[radner]

For sure it's better for them to be on the same side, due to the fact that a normal via has got a very thin conducting layer.
That would mean quite a lot of parasitc resistance. But you could put a wire trough the via and solder it on both sides, this should
aid the problem, if their is any at all. For sure this is not ideal for EMI and overall high frequency performance of the board but long traces are
at least as worse like one via.

And for stable operation in rough environment at high freqeuncies we would have to switch to a 4 layer PCB to get a full GND and VCC plane,
but I don't think that this is the approach of this project and the layout should work for labratory use.

The only stability problem I see are high frequency signals near the crystal oscilators, like the USB nodes. All other high frequency signals should be
avoidable as far as I see that.

[kmmankad]

yes,I share that concern.I guess we should route them away from the crystal,since we do have space,though that will increase their lengths(hope its not a problem).I'll do those changes tonight.

[radner]

I don't see a problem with longer USB traces as long as they have the right characteristic impedance, which for USB is 90 ohms from D+ to D-.
Unfortunately I don't have an idea who this is achieved on the board.
I couldn't find any routing rules for this, you may should search the net a bit.

[kmmankad]

I found some routing and layout guidelines from the official usb site, and a quick read of the checklist given at the end(Page 17) brings out many problems in this current layout.

High Speed USB Platform Design Guidelines http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf

I propose we should do 2 things,
1.Not route 12[0] and 12[1],since thats causing a ground plane break beneath our USB signals.
2.Use an external oscillator arrangement which does not require capacitors,so we get some space between the crystal and the USB lines.
(I'm specifically keeping this http://in.element14.com/murata/cstcw24m0x53-r0/resonator-smd-24mhz/dp/1401654 as a prime replacement candidate,but I'm not able to find its eagle footprint.)
...impedance as you said should be 90 ohms between them.I'll try and calculate those when I get some free time after my exam tomorrow.

[radner]

Allright this should work.

I would place the Oscillator at the bottom side of the PCB, for example we could use something like this http://www.abracon.com/Oscillators/ASV.pdf

The easiest thing to make the traces shorter would be to use a angled usb connector like this http://at.mouser.com/ProductDetail/Harw ... WdWbf8M%3d, so we could place the connector way tighter to the chip as done now.

Good Luck for your exam tomorrow

Best Regards
Phillip

[kmmankad]

Since this is only the first version,I'm also thinking of the option of not having the external crystal,since only the CY8CKIT-030 uses one,i.e none of the starter kits,or even the CY8CKIT-001 uses a Mhz crystal,so that points to the stability of the internal clocking,which we can also safely acknowledge,by not using one.That said,I am keeping pads for a through hole resonator,for testing,but it is not intended for active use.

I dug into this impedance issue,ran the formulae I found,and tried tweaking the design,but I am not able to get it to match the required 90 ohms value,even with its 15% allowed error.After some more google-ing,I'm starting to think its not that important.I saw a few more stable designs today,that have not even the remote-est form of "USB Routing".Infact I noticed a number of flaws in their design(s)(DP,DM lines criss crossing other signals at 90,jumping layers and not parallel to each other at all,passing over multiple breaks in the ground planes,etc),but apparently those dont interfere much,and their boards are quite stable.