by bobby on Tue Jan 19, 2010 11:45 am
Sorry for my delayed reply. I had tracked down the PowerPSoC answers prior to the holiday break, but I forgot to post, and this totally slipped my mind when I got back. Obviously some of these are dated, as they were asked pre-public launch of PSoC 3 and PSoC 5. Here you guys go:
Q: Will the current generation of PSoC part numbers be "not recommended for new designs" with the launch of PSoC3 and PSoC5?
A: No, we have no plans to discontinue or "no longer recommend" PSoC 1 devices, in fact we just recently released some new ones. Our belief is that PSoC 3 functionality picks up where PSoC 1 left off, and that the devices really don't overlap.
Q: The speculation has been that PSoC3 is based on an 8051 core, is this true and does this mean that the M8C has been dropped?
A: PSoC 3 architecture is indeed 8051 based. Our PSoC 1 architecture is still based on the M8C.
Q: In the January earnings call PSoC5 was described as a 32-bit architecture, what processor core will be used?
A: PSoC 5 has an ARM Cortex-M3 (which I doubt is news to anyone now).
Q: When can we get samples of PSoC5?
A: We are sampling PSoC 5 to select customers today, and our broad-based sampling will begin in Q2 2010.
Q: What packages will be available?
A: 100-pin TQFP, 68-QFN, 48-SSOP (and 48-QFN for PSoC 3).
Q: Will PSoC5 accept code generated by the standard gcc compiler?
A: PSoC Creator, the development environment for PSoC 5, ships with an installation of the GCC compiler and associated tools. The operation of PSoC 5 with this version of the GCC toolflow is the supported flow for use of PSoC 5 with GCC.
Q: Will PSoC5 have the MPU (memory protection unit?)? Will it be able to run uClinux or perhaps full Linux?
A: The Memory Protection Unit (MPU) is an optional feature of the Cortex-M3 architecture. PSoC 5 does not include the MPU option. Future devices in the PSoC 5 family may add support for the MPU. An MPU is not a feature required for uClinux. The main issue with running uClinux on PSoC 5 is the system memory requirements. The largest PSoC 5 device has 256 KB of Flash. A typical program built for uClinux on an ARM architecture exceeds 256 KB and full Linux applications will be much to large. A better open source operating system choice for PSoC 5 is FreeRTOS. There are also several commercial RTOS products that are a great fit for the Cortex-M3 architecture such as Micrium's uC/OS-III or Segger's embOS.
Q: Will there be an ARM instruction set version of something like the PowerPSoC ?
A: This functionality is currently on our roadmap.
Q: Will you make a PowerPSoC that can drive a H bridge?
A: This functionality is currently on our roadmap.
Q: Will any version of the PSoC3 or PSoC5 or PowerPSoC be available in a DIP package?
A: There are no plans to introduce a DIP package at this time, however we are constantly evaluating the requests of our customers, and if we see enough activity for a DIP package, this is something that could happen.
Q: Will there be an ethernet controller onboard, I am not sure if that is a standard feature of the M3 core?
A: There is not an ethernet controller on board. We will be partnering with some venders to offer a solution, and we are looking into adding ethernet in a future PSoC 5 device.
Q: Will the 12 bit DAC which is part of the SAR ADC be available for use by the user.
A: We do not offer a component that gives the user access to this internal DAC.
Q: what is the speed of this DAC if its available.
A: Not available, however if you need a DAC with higher than 8-bit resolution, there are ways to accomplish this with the 8-bit DAC and UDBs.
-Bobby
