PSOC Square wave generation

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PSOC Square wave generation

Postby sherby » Sat Nov 30, 2013 5:56 am

I wish to create a 100khz square wave from my PSOC. Any suggestions on how I should go about it?
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Re: PSOC Square wave generation

Postby bobmarlowe » Sat Nov 30, 2013 10:47 am

Take a timer usermodule and feed it with a clock of 16 MHz, set the period to 160-1 and the compare-value to 80-1. Then the compare-output will run at 100kHz 50% duty-cycle.
You may as well use a PWM-Usermodue (which can give you 2 different clocks) or a counter.


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Re: PSOC Square wave generation

Postby danadak » Sat Nov 30, 2013 4:38 pm

Simply place a clock component on schematic, and set its properties to 100
Khz. Buffer it with a simple gate if you need it to handle high fan out.

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Re: PSOC Square wave generation

Postby sherby » Sat Nov 30, 2013 6:28 pm

If I am to drive an external LED with it(saying at 1Hz)., Can I simply use the Clock to do it?
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Re: PSOC Square wave generation

Postby bobmarlowe » Sun Dec 01, 2013 1:17 am

A pin can sink 8mA, so depending on your VCC you ought to use a limiting resistor. (VCC - VLED)/5mA = (5V - 1.7V)/5mA = 660 Ohms.

Dana's approach is the most simple, using nearly no resources. Using a timer gives you the ability to change programatically fre4quency and duty-cycle over a wide range.


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Re: PSOC Square wave generation

Postby danadak » Sun Dec 01, 2013 6:05 am

If you need more LED current you can parallel a few simple gates, or
if not using SIO pin which has a 25 mA sink rating use that. There is a limit
on quadrant total current of -

PSOC GPIO Port Ratings.jpg
PSOC GPIO Port Ratings.jpg (91.27 KiB) Viewed 1892 times


In applications where the typical current sourced and sunk
by the GPIO pins is expected to be greater than 80% of
the limit, it is recommended that attention be given to
ensure that no single quadrant of GPIO pins will exceed
their maximum limits under the worst operating conditions.
This may mean that the design must use pins in separate
VDDIO quadrants to spread out the current.


The approach to just using a clock does use resources, just not UDB resources.
There is a limitation on how many dividers each clock uses for the requested freq
and # clocks you can place on a schematic.

http://www.cypress.com/?rID=57571 AN72383 PSOC GPIO

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