Multi-microprocessor communications advice

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Multi-microprocessor communications advice

Postby eg2ah » Mon Mar 18, 2013 3:35 pm

Hi,

I am looking for some advice / suggestions regarding a multi-microprocessor bus / communications interface; I have several design constraints which makes this a little difficult:

1. Slaves must auto address from the master sequentially
2. I only have 3 I/O lines to design the bus around
3. The bus needs to run at approx. 400KHz
4. Needs to be able to connect 20-30 salves to one master
5. Needs to operate in an industrial environment.
6. Slaves are connected using board to board connectors and are no more than 25mm apart.

The first option I looked into is i2c, using SCL and SDA as the bus, and the third pin to indicate interrupts (I will call this INT from now on) from the slaves (i.e. the slaves could simply pull the line down). Each slave would have a NXP hot swappable bus driver (PCA9514AD) attached for protection and reduced bus capacitance also providing the ability to disconnect the slave from the bus using the OE pin.

Each slave would also have the ability to break the INT line using a relay (as silicon switches will have an ON resistance which will cause me issues due to the number of slaves I will have), the relay would be normally closed. Upon system start-up the slaves will all have a zero address and would disconnect themselves from the bus and break the INT pass through connection (by enabling the relay).

This would leave only the first device connected to the bus the ability to see the INT pin status from the master, thus when the master pulls the INT line low the first slave connects to the i2c bus gets an address from the master and connects the INT pass through (by allowing the relay to close). This then signals the next slave to enable the i2c bus and get an address from the master, this continues until all slaves have been addressed. The master can then release the INT pin and the slaves are then able to use it to signal the master when interrupts have occurred.

NOTE; I will try and post a block diagram of the i2c bus for better clarity.

The second option which I think is possible better is to use the UART in 9bit mode (paragraph taken from a PIC manual):

A typical multiprocessor communication protocol will differentiate between data bytes and
Address/control bytes. A common scheme is to use a 9th data bit to identify whether a data byte
Is address or data information. If the 9th bit is set, the data is processed as address or control
Information. If the 9th bit is cleared, the received data word is processed as data associated with
The previous address/control byte.

The protocol operates as follows:

• The master device transmits a data word with the 9th bit set. The data word contains the
• Address of a slave device.
• All slave devices in the communication chain receive the address word and check the slave
• Address value.
• The slave device that was addressed will receive and process subsequent data bytes sent by
• The master device. All other slave devices will discard subsequent data bytes until a new
• Address word (9th bit set) is received.

The circuit diagram for my bus is as follows:

Image

The sequential addressing would simple work by broadcasting a message to make each slave set their address to zero which in turn would make each slave disable there logic buffers, thus stopping the bus from moving past the first connected device, once the first device is addressed it’s buffers would be enabled and the second slave would be addressed and so on until all slaves are addressed.

The interrupt line in this case would be unidirectional and be used to indicates a slave has an interrupt pending, to avoid polling.

If anybody can offer any opinion’s or advice I would be grateful, at the moment i am leaning towards the UART option as it is lower cost and the serial data lines are easier to buffer than i2c, which will hopefully make them less susceptible to noise. The only issue is the tolerance on the baud rate for each slave.

Thanks,
eg2ah
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Re: Multi-microprocessor communications advice

Postby danadak » Wed Mar 20, 2013 1:51 am

You might consider posting this at http://www.cypress.com/?app=forum&source=header
Post it in Creator forum.......?

Clearly you have no physical layer issues per se, except for slave disconnect. Eg. UART
would not need 232 signaling.

Not sure if this will help, interesting reference -

slla067b.pdf
(1.75 MiB) Downloaded 124 times


Regards, Dana.
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Re: Multi-microprocessor communications advice

Postby DavidCary » Sun Jun 16, 2013 6:38 am

Sounds like an interesting project.

The Electronics stack exchange "Help with device identification in a chain"
suggests many different protocols that start with initially identical slave devices,
and as the protocol runs the devices learn their position along the chain and use that position number as an ID number.
Perhaps one of them will work for you or be close enough that you can get it to work with a few changes.
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