processor-processor communications opinions

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processor-processor communications opinions

Postby eg2ah » Wed Apr 24, 2013 1:20 pm

Hi,
I have an application where I need a reliable processor-processor communications bus over two wire. That can self-address and run at around 400 KHz. It needs to support up to 20-30 slave devices and one master.

Image

Leaving I2C aside for a moment (I will discuss why the implementation is a pain for my application later). I was looking at using 9bit serial buffered through high speed CMOS non inverting bus buffers (propagation delay is around 5ns (max)).
The 9th bit is set high if the data packet contains an address and is hardware matched in the processor I am using, such that the USART is not forever interrupting the processor as packets are sent.

Self-addressing would be achieved by, each slave starting with address zero and the buffer of each slave disabled, such that only the first salve see’s information from the master, the master will then assign the first slave address 1 at which point the buffer is enabled and the second slave can be assigned and so on until all slaves are addressed.

Can anybody see any issues with this idea? (Hardware wise)

Buffering from each board adds a small propagation delay which should not matter, the transmission line is kept small (i.e. between each board) and if I have noise / capacitance issues I can always drive the buffers harder (by decreasing the pull-up resistors).

The only issue I can see (although it is late can I am tired), is that temperature differences between slaves (although they are interconnected and only 25mm apart) could alter the crystal / clock on each micro such that I could get framing errors etc. (but this could be compensated for in firmware)

Thanks,
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Re: processor-processor communications opinions

Postby daveinterrupted » Wed Aug 28, 2013 7:55 pm

Easy way to handle this is with hardware:

Use I2C.

Use Address 0xAA as the LISTEN address that all slaves will powerup and listen to.

Set each slave's hardware to power up into a "man-in-the-middle":

[M] -------- [SL1]-X--------[SL2]-X-------[SL3]-X-------- ETC.

In this network topology, on powerup, the master can only communicate with SL1.

The master will look for an ACK when it writes a byte (0x0F) to slave address 0xAA.

SL1 will default to address 0xAA on powerup, SL1 will receive the byte and ACK it. The byte received (0x0F) is the new virtual address for SL1. SL1 will now only respond to address 0x0F and NOT to 0xAA anymore.

SL1 will now also activate a relay or mosfet or other switch to set itself up as a "T"drop in the network.

[M] -------- [SL1]----------[SL2]-X-------[SL3]-X-------- ETC.

This will allow the the master to communicate to the next slave, [SL2] which is listening on address 0xAA, or to [SL1] which is listening on address 0x0F.

Master will again write a byte (0x10) to slave address 0xAA and look for an ACK.

Note that 0x10 is( 0x0F + 1), the slave address incremented for the next slave.

SL2 will default to address 0xAA on powerup, SL2 will receive the byte and ACK it. The byte received (0x10) is the new virtual address for SL2. SL2 will now only respond to address 0x10 and NOT to 0xAA anymore.

SL2 will now also activate a relay or mosfet or other switch to set itself up as a "T"drop in the network, rather than as a single point-to-point.


This will continue until Master sends out a byte and looks for an ACK that never arrives. This means that the Master has addressed all of the slaves that it can address and it's effectively reached the end of the line. This also means that the master knows how many slaves are attached, the physical order of the slave connections, etc. Should a failure in the system occur, the master could poll each address by looking for an ACK to find where the breakdown occured.



Just an idea...



Effectively you start out with an I2C bus with only 1 master and 1 slave that are physically connected to each other. As each slave gets a new virtual address that it will listen to, that newly addressed slave will connect the bus to the next slave. The master will then address the newly connected slave and give it a new virtual address, etc. until all slaves are given a virtual address.
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Re: processor-processor communications opinions

Postby danadak » Thu Aug 29, 2013 5:19 am

That would make an excellent ap note, seems adaptable to SPI as well.

Regards, Dana.
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