CRC Component doesn't match firmware lookup table

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CRC Component doesn't match firmware lookup table

Postby Dagodevas » Sat Feb 23, 2013 6:02 pm

I am being driven insane by this one. I have been using a firmware function and lookup table to calculate my 8-bit CRC for my Maxim DS18B20 1-Wire interface. The result I get from this function matches the result of an online CRC calculator and the CRC that is generated by the DS18B20 itself. I am now trying to accomplish the CRC calculation using the CRC component. The polynomial is X8+X5+X4+1. I have tried shifting the bytes into the CRC from a custom component as well as a SPIM. Both of which produce the same, wrong result out of the CRC component. I haven't seen any mention of quirky behavior of the CRC, but perhaps I just missed it. Anyone else have any issues like this or can suggest what to try next? With the SPIM, I have tried transmitting MSB first and LSB first. I am using SPI mode 0 (MOSI signal changes on falling clock edge).
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Re: CRC Component doesn't match firmware lookup table

Postby Dagodevas » Tue Feb 26, 2013 10:48 am

I think I have figured out the problem. It looks like Maxim uses the opposite bit order for the CRC result from what is standard. I don't know enough about CRC in general to understand why they would do something like that. Anyone have any ideas? Also, is there an easy way anyone can think of to reverse the bit order of the CRC component output to make it compatible with the Maxim LUT? Can I just convert the polynomial to some other form?
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Re: CRC Component doesn't match firmware lookup table

Postby Dagodevas » Thu Feb 28, 2013 5:39 pm

It seems that what Maxim does for the CRC is not necessarily an oddity. Some CRCs are implemented with a right shift (LSb first, usually used on serial data that is sent LSb first like RS-232), some with a left shift (MSb first). The datapath CRC feedback path in the PSoC3 is hardwired for a left shift configuration. Fortunately, after an embarrassing amount of head scratching, I figured out it's really not too difficult to implement a right shift CRC in a datapath with some very basic verilog.
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