Signal Conditioning and Amplification

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Signal Conditioning and Amplification

Postby skatemic » Tue Feb 12, 2008 8:35 pm

Hi Guys,

I am trying to filter and amplify an analog differential voltage produced from a wheatstone bridge of strain gauges. I need a total gain of 10000 and I need a low pass filter with a break frequency of 10Hz.

Is there an easy way to do this in PSoC designer? I tried tying the output of a INS AMP to a low pass filter and then tying the output of the lowpass filter to PGA but was unsuccessful at tying the outputs of each block to the inputs of the next.

Could someone please explain to me how to do this? Or tell me if I am going about this all wrong.

Thanks.
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Postby Debbieg » Wed Feb 13, 2008 4:39 pm

Hell, yes, you and the PSoc can do this. Once you are done with the user module selection go to the interconnect view. Left click on the input or output pin of the module and pick from the list where you want to connect it to. I just wired an example like this, it's simple and fun.
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Postby bakat_sakuragi » Wed Feb 13, 2008 5:19 pm

Hi skatemic,
Can you post your block diagram and code?
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Filtering and Amplification

Postby skatemic » Wed Feb 13, 2008 5:53 pm

Here is my project file.

I am trying to amplify the difference between two voltages supplied to the PSoC.
Am I going about this the right way?

I cannot figure out how to run the differential output of the INSAMP to the input of the lowpass filter and then run the output of the filter to the input of 2 cascaded PGA's . The overall gain I would like to achieve is 10000.



Thanks for the help!
Attachments
INSAMP_TEST.zip
(15.38 KiB) Downloaded 300 times
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Postby skatemic » Wed Feb 13, 2008 5:54 pm

Debbieg wrote:Hell, yes, you and the PSoc can do this. Once you are done with the user module selection go to the interconnect view. Left click on the input or output pin of the module and pick from the list where you want to connect it to. I just wired an example like this, it's simple and fun.


Do you think you could post your project files?

Thanks for the help!
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Postby bakat_sakuragi » Wed Feb 13, 2008 8:16 pm

I am trying to amplify the difference between two voltages supplied to the PSoC.
Am I going about this the right way?


I am trying to amplify the difference between two voltages supplied to the PSoC.
Am I going about this the right way?


Hi..
If you want to amplify the difference it think maybe you need :
1. Add DualADC. Add DAC.
2. Add LCD.
3. Add 2 PGA UM.PGA gain is set to 1.
4. Connect each PGA to DualADC. So you will get result for voltage 1 and voltage 2 displayed in LCD.
5. In the program main.c you can calculate to get difference voltage. Lets says
voltage 2 -voltage 1 = voltage needed.
6. Pass the data to DAC9. Output from DAC 9 connect to PGA and set the gain
as you want.

Hmm, this is just idea... Maybe someone have a better idea..
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Postby jiml » Thu Feb 14, 2008 5:56 pm

If you are successful in stringing together a chain of amplifiers to get a gain of 10,000 I think you will be unhappy w/ the result. Consider that the INSAMP has an input offset voltage of up to 3.5mV. If you use the maximum gain setting for the INSAMP (roughly x100) you will now have in input offset of 350mV. By the time you amplify this by another 100 you will have an output voltage of 35V(!) which means the output voltage of one of the amps will have saturated due to the input offset alone.

The same for noise. Each stage of amplification will amplify the noise from all the prior stages and will then add a bit of its own noise and offset.

If your application really needs this much gain, you might consider ...
a) get a more sensitive bridge sensor
b) Apply a larger excitation voltage/current to the bridge. Most bridge sensors are specified in terms of mV/V (ie mV of output per volt of excitation) at full scale input. Bigger excitation == more signal but watch out for too much power dissipation in the bridge which can cause self-heating and thermal drift
c) If you are planning to digitize the bridge output, look at using a good 24bit external ADC. They can be had in small packages with SPI comm. links and will hook to your pSoc very nicely.
d) Try applying a bipolar excitation to the bridge and use correlated double sampling to subtract out the offset voltages in the intermediate ampliers (assuming they don't saturate!).

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Postby nan358 » Fri Feb 15, 2008 9:19 am

As jiml has mentioned (that suggestions are so practical!), DC coupled amplifier with that much of total gain will easily saturate by its own offset voltage.

This is just an untried thought and a play of figures, but if the bridge can be driven with switching voltage/current (not necessarily bipolar), intermediate offset voltage may be rejected with BPF and/or synchronous rectifier.

Modules may be connected and configured like this:
  • Place INSAMP, BPF2, SCBLOCK, PGA_1, LPF2, PGA_2, and ADCINC12. Route them in that order.
  • Configure SCBLOCK as a pass-through buffer. This is used to feed PGA_1 from BPF2 only.
  • Configure LPF2 as a filter with a synchronous rectifier. Appnote AN2044: Signal Rectification, using Switched Capacitor Modulators may be applicable with a small modification.
  • In order to compensate delay difference between LPF2 signal and synchronous rectification clock, the clock may need to be delayed. That delay may possibly implemented with digital blocks. Or, PSoC may generate and provide two phase clocks, one for switching bridge power supply and the other for synchronous rectification. In the latter case, appnote AN2345: Simple Method to Generate Digital Signals with Variable Phase Shift Between seems applicable.

INSAMP has typical DC input offset of 3.5mV. When it's gain is set x100, its DC output offset will be 3.5mV x100 = 350mV, but this DC offset will be cancelled by the next BPF2 . Assuming the sensor output signal is 0.1mV p-p differential, the effective output signal here will be 0.1mV x100 = 10mV p-p single end.

BPF2 itself has typical DC offset of 28mV. SCBLOCK may also have about the same offset (pure speculation), and next PGA ( PGA_1 ) 4.5mV. When the gain of PGA_1 is set x24, DC output offset of PGA_1 will be the total input offset (28mV + 28mV + 4.5mV) x24 = 1.45V. This DC offset will again be cancelled out by the next LPF2 because it does synchronous rectification. The effective output signal here will be 10mV x24 = 240mV p-p.

LPF2 has typical DC offset of 18mV. The effective output signal here will be about 150mV (not p-p, but steady from AGND), because the 240mV p-p signal will be rectified and filtered.

Next PGA ( PGA_2 ) has typical DC input offset of 4.5mV. When the gain of PGA_2 is set x8, DC output offset of PGA_2 will be (18mV + 4.5mV) x8 = 180mV. The effective output signal will be 240mV x8 = 1.92V.

The remaining DC offset of 180mV may be removed by software based calibration. There will be a large gain error, so a software based calibration will be necessary anyway.

--
Nobu
Attachments
amp.jpg
Example Routing
amp.jpg (39.8 KiB) Viewed 6864 times
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Postby jiml » Fri Feb 15, 2008 10:55 am

I think that Nobu's approach is sound. Certainly modulating the signal (ie driving the bridge with an time varying signal) and then band limiting around the drive frequency is a good approach.

Either way...when you get to the ADC stage, I would also recommend that you use the smallest Vref that your ADC will tolerate and that the Vref be derived from the bridge excitation voltage (possibly by dividing w/ fixed resistors). This will ensure that if the supply voltage drifts, the bridge output and Vref will change by the same proportional amount and you will not pick up errors from that.

Unless the performance of the UM's in Nobu's diagram are very temperature and supply voltage stable you may still run into trouble....but that goes for pretty much any component in the signal chain. W/ very high resolution ADCs you can even see small thermoelectric potentials created by temperature gradients on the PCB and the wire/solder/trace metal junctions within the circuit board. These can sometimes amount to several uV so at your target gain of 10,000 you could see mVs!

Measuring very small signal's is hard!

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Postby nan358 » Thu Feb 28, 2008 6:34 am

I made a try, using a PSoC Express World Tour evaluation board and a resistor network. The setup was powered by USB 5V, and was without additional shields, external buffers/amplifiers, and external filters.

I prepared a resistor network as to output 0uV to 100uV differential (set by a pot) when driven at 5V. It was driven directly by PSoC's two digital outputs at 10kHz, 50% duty, and 180 degrees out of phase. This made the output signal up to +/-100uV differential, or up to 200uV p-p differential.

The internal module layout/connection I actually used differs a bit from what I had previously posted. I omitted a LPF because the ADCINC itself works as a low pass filter. I also omitted the second PGA (note that the PGA2 in the attached diagram is not in the signal chain) because the necessary total gain is achievable without it by setting BPF gain. Since the removed LPF also works as a synchronous detector, an SCBlock is added to do synchronous detection.

The theoretical gains for each stages are: 93 for INSAMP, 38 for BPF, 5.3 for PGA, and 1.1 for SCBlock. The input signal is rectangular and only the fundamental frequency component of it passes BPF. The ratio of the fundamental frequency component level to the rectangular signal level is 0.79. The ratio of the DC average of fully rectified signal to the original sinusoidal AC signal level (p-p) is 0.32. The overall theoretical gain from AC p-p to DC is thereby calculated as 5,200. This gives to the ADC input 0mV to 1,040mV DC signal for 0uV to +/-100uV differential input, again theoretically.
Attachments
setup.jpg
Test setup
setup.jpg (27.32 KiB) Viewed 6629 times
uVtest.gif
Resistor network schematic
uVtest.gif (3.84 KiB) Viewed 6627 times
blocks2.jpg
UM diagram
blocks2.jpg (32.01 KiB) Viewed 6630 times
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Postby nan358 » Thu Feb 28, 2008 6:37 am

I set the Vref setting as (VDD/2)+/-(VDD/2), and I limited the ADC input signal swing within AGND+/-(Vref/2), or 2.5V+/-1.25V when VDD is 5V, because I didn't want to let internal analog blocks to swing output near the rail. This limitation effectively reduced the ADC resolution by one bit. The detector output was supposed to be non-negative relative to AGND. This also reduced the resolution by another one bit. As I set the ADC (ADCINCVR) resolution as 13 bits, the effective resolution was 11 bits. This reduction of resolution may be avoided by providing proper Vref externally.

The first attachment is the scope traces of the INSAMP output (blue) and the BPF output (red) when the pot was set to maximum. INSAMP output reads about 20mV p-p and BPF output about 600mV p-p. The ADC reading was about 2,000, which corresponds to the ADC input of about 1,220mV above AGND. These values agree, in my sense, with the respective theoretical values.

The A/D conversion rate was set to 5 sps, and a 32-sample moving average was implemented. As it requires 6.4s (32 samples / 5 sps) to update all samples to be averaged, a quick change of the A/D input takes 6.4s to be fully reflected to the averaged result. (See upper chart of the second attachment. "samples count" is the time elapsed in seconds.)

In the upper middle is the raw ADC reading ranges and the averaged results for five minuts when the pot was set to the maximum. In the lower middle is one when the pot was set to its minimum. In either chart, the error of the raw ADC readings looks to be about +/-12 LSB, and the error of the averaged results looks to be below +/-2 LSB.

The ADC readings drifted easily as the ambient temperature changed. In the lower is the readings when I stopped the room heating and opened window to lower the ambient temperature. The same kind of drift happened when the set was cold started.

--
Nobu
Attachments
trace1.gif
Scope traces
trace1.gif (11.68 KiB) Viewed 6628 times
uVtest2.gif
Readings charts
uVtest2.gif (48.04 KiB) Viewed 6632 times
uVtest2.zip
Test application
(122.93 KiB) Downloaded 256 times
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Re: Signal Conditioning and Amplification

Postby jamesjun » Mon Aug 24, 2009 11:06 pm

Nobu san. I figured out what the problem was. The problem is the power of PGA has to be set LOW. High power output distorts the signal and when i feed 1k sine wave in, i get a noisy output with high frequency noise added.

For anyone who is reading this forum, don't forget to set

PGA_1_Start(PGA_1_LOWPOWER);

when you use external feedback resistors for the purpose of using CT blocks for general puropse op-amp.
You don't have to change pin power output settings and leave it as default "high Z analog"
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Re: Signal Conditioning and Amplification

Postby signum » Wed Jul 04, 2012 1:48 am

Hi,

I want to measure strain gauges on a PSoC5 device (Cy8C5568) very much like the project described above. Any ideas?

Regards,
Kirs
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Re: Signal Conditioning and Amplification

Postby danadak » Wed Jul 04, 2012 2:32 am

Here is a thread in another forum discussing IAs.

http://www.psocdeveloper.com/forums/viewtopic.php?f=42&t=8692

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Re: Signal Conditioning and Amplification

Postby danadak » Wed Jul 04, 2012 2:43 am

Another approach is correlated double sampling, an ap note
and project attached.

AN2226_CDS.zip
(635.79 KiB) Downloaded 120 times


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